Nilesh Patidar
Assistant Professor
PUBLICATIONS
There are a lots of publications in International Journals and Conference/Academic Publications.
Academic/Conference Publications
Design of Adder/Subtractor using Reversible DKG Gate in QCA
Abstract-Quantum computers for the efficientsimulation of physical systems are emerging today. Reversible logic has extensive applications in quantum Computing. Reversible logic is widely being considered as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy. Reversible gates such as Fredkin and DKG gates can be of great use for the implementation of the logic designs. In this paper, a design constructing the adder - Subtractor based on reversible DKG gate as logic components using QCA is proposed. By using reversible logic gates instead of using traditional logic gates such as AND, OR, XOR, NOT, whose function is the same as the traditional Adder and Subtractor are designed.
Design of 1-bit Reversible ALU Using Proposed NN Gate and DKG Gate and its Implementation in Quantum-Dot Cellular Automata
Abstract-– Conventional digital circuits dissipate a significant amount of energy because bits of information are erased during the logic operations. Under ideal conditions, Reversible logic gates produce zero power dissipation. So these can be used for low power design. Thus, if logic gates are designed such that the information bits are not destroyed, the power consumption can be reduced dramatically. The information bits are not lost in case of a reversible computation. This has led to the development of reversible gates. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. By provided the corresponding control unit, the proposed Reversible 1 bit ALU using NN Gate & DKG gate can combine the classical arithmetic and logic operation in a reversible integrated system. Proposed reversible NN gate performed logical operation such as AND & OR and Reversible DKG Gate performed Arithmetic operations such as Addition & Subtraction and its implementation in QCA. This paper provides a threshold to build more complex arithmetic logic unit using reversible logic. Simulations have been carried out using the QCA Designer, a layout and simulation tool for QCA.
8-Bit Arithmetic Logic Unit Implementation in Quantum-dot Cellular Automata (QCA)
Abstract-Semiconductor industry has achieved almost exponential scaling down in feature size for pastfew decades. However it will be very hard to sustain the trend using conventional lithography based VLSI technology. To replace conventional CMOS technology, broad and extensive researches have been done at nano-scale in recent years. Among the emerging technologies, Quantum-Dot Cellular Automata (QCA) plays an important role not only because it gives a solution at nano-scale, but also offers a new methodology of computation and information transformation. In terms of feature size, it is claimed that the size of the basic QCA cell can achieve few nanometers fabricated by molecular implementation at room temperature. Quantum-Dot Cellular Automata (QCA) is a new technology for nano-electronic computers. It provides high density, high switching speed, and ultralow power dissipation. We describe the design and layout of a simple 8-bit Arithmetic Logic Unit (ALU) based on quantum-dot cellular automata (QCA) using the QCADesigner design tool. The ALU design is based on combinational circuits which reduces the required hard-ware complexity and allows for reasonable simulation times. Our aim is to provide evidence that QCA has potential applications in future computers provided that the underlying technology is made feasible.The Paper Proposed design of 8-bit Arithmetic logic unit (ALU) and implementation in QCA which consist arithmetic unit, logical unit and ripple carry adder are major blocks of 8-bit ALU. The simulation result of 8-bit ALU is verified using QCADesigner tool.
Comparison Between the Design of Various Logic Gates Using QCA & CMOS Technology
Abstract-Quantum Dot Cellular Automata (QCA) is a new technology which overcomes the limitations of CMOS. Quantum Dot Cellular Automata (QCA) is an advanced nanotechnology that revolves around the single electron position control. QCA aims to work for the faster technology with the development of the faster computer with smaller size & low power consumption. The researchers & scientists all over world are trying very hard to find out the alternative solution for chip layout designing & fabrications. QCA is one of the most interesting and fast upcoming nanotechnologies. It is a solution for layout designing which is able to design various digital circuits in the range of 9nm to 18nm. In this paper, we have given a comparative study of various basic gates such as AND, OR, NOT etc. Here, we compared the designing of these circuits using CMOS and Quantum Dot Cellular Automata (QCA). Our aim is to establish the fact that QCA technology is highly feasible for future computers.
Journal Publications
Design of Hybrid Adder Subtractor (HAS) using Reversible Logic Gates in QCAechnology
Abstract-Quantum computers for the efficient simulation of physical systems are emerging today. Effect of Spin on Quantum Dots (QDs) paved the way for QCA. Quantum-dot cellular automata (QCA) have a simple cell as the basic element. The cell is used as a building block to construct gates and wires.Reversible logic has extensive applications in quantum Computing. Reversible logic is widely being considered as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy. Reversible gates such as Fredkin and DKG gates can be of great use for the implementation of the logic designs. Recent advances in reversible logic allow for improved quantum computer algorithms and schemes for corresponding computer architectures.In this paper, a design constructing the hybrid adder - Subtractor based on reversible logic gates as logic components using QCA is proposed. By using reversible logic gates instead of using traditional logic gates such as AND, OR, XOR, NOT, a Hybrid reversible Adder - Subtractor whose function is the same as the traditional Adder and Subtractor are designed and compared with the functioning of DKG gate based adder-subtractor. The simulation results shows that higher speed, smaller size and lower power consumption can be achieved with the proposed HAS system.
Design of One Bit Arithmetic Logic Unit (ALU) in QCA
Abstract-Quantum cellular automata (QCA) is a newtechnology in nanometre scale as one of the alternative to nano technology. QCA technology has large potential in terms of high space density and power dissipation with the development of the faster computer with low power consumption. We describe the design and layout of asimple 1-bit ALU based on quantum-dot cellular automata(QCA) using the QCADesigner design tool. The ALU design is based on combinational circuits which reduces the required hard-ware complexity and allows for reasonable simulation times. Our aim is to provide evidence that QCA has potential applications in future computers provided that the underlying technology is made feasible. We have design certain combinational circuit by using Majority gate, AND, OR, NOT, X-OR in QCA. In the combinational circuits, we have design Logical Extender, Arithmetic Extender and Full Adder are major blocks of one bit ALU.
A Novel 4-bit Arithmetic Logic Unit Implementation in Quantum-Dot Cellular Automata
Abstract-Quantum cellular automata (QCA) is an advanced nanotechnology that attempts to create general computationalat the nano scale by controlling the position of single electrons. QCA technology has large potential in terms of high spacedensity and power dissipation with the development of the faster computer with smaller size & low power consumption.The logic design of ALU, an important constituent part of CPU, is described in this paper. A design constructing 4-bitArithmetic Logic Unit (ALU) based on the QCA (Quantum-Dot Cellular Automata) is presented. The proposed 4-bitArithmetic Logic Unit is simulated using the QCADesigner tool and experiment result shows that the arithmetic & logicalfunction of the designed circuit is correct. Our aim is to provide evidence that QCA has potential applications in futurecomputers provided that the underlying technology is made feasible.
Basic Reversible Logic Gates and its QCA Implementation
Abstract-Reversible logic has various applications in various field like in Nanotechnology, quantum computing, Low power CMOS, Optical computing and DNA computing, etc. Quantum computation is One of the most important applications of the reversible logic.Basically reversible circuits do not lose information & reversible computation is performed only when system comprises of reversible gates. The reversible logic is design,main purposes are - decrease quantum cost, depth of the circuits & the number of garbage output. This paper provides the basic‘s of reversible logic gates & its implementation in qca.
Design and Implementation of 16-bit Arithmetic Logic Unit using Quantum dot Cellular Automata (QCA) Technique
Abstract-Quantum Dot Cellular Automata (QCA) is an advanced nanotechnology that attempts to create general computational at the nano-scale by controlling the position of single electrons. Quantum dot cellular automata (QCA) defines a new device architecture that permits the innovative design of digital systems. QCA technology has large potential in terms of high space density and power dissipation with the development of the faster computer with smaller size & low power consumption.QCA help us to overcome the limitations of CMOS technology. In this paper, A design 16-bit arithmetic logic unit (ALU) based on the Quantum dot cellular automata (QCA) is presented. The simulation result of 16 bit ALU is verified using QCA Designer tool.
PLC Based Automatic Sequential Process Control System
Abstract-Programmable logic controllers are extensivelyused in industries for controlling sequence of actions of theprocess. The sequence of process flow is decided forcontrolling the parameters like level, flow, weight andtemperature. The brain of the system is PLC. Appropriatehardware for interfacing the process to the controller isdeveloped for controlling the level ant temperature of theprocess. For controlling sequence of actions ladder diagramis developed. Programmable Logic Controller (PLC) isdesigned to operate in real time environment. It has beenobserved that in many industries distributed control systemand PLCs are extensively used. PLC based sequential batchprocess control (PLCSBC) is a laboratory type setup. Thissetup will be useful for demonstrating the use of PLC insequential control operations in industry and development ofladder diagram for particular application. The system underconsideration is designed to carry out sequence of events.The process under consideration is Batch process, which iscontrolled by PLC.
Investigating the Effect of Motion Blur and Gaussian Noise in Image and Comparative Analysis of Various Filter for Reconstruction of Image
Abstract-The present work investigates the qualitativeeffects of the Gaussian noise in image called "Gaussianblur”. Noise is inherent to the physical process of dataacquisition so to analyze the image proper filteringtechnique is required. To do this segmentation process ishelpful but it requires long time to process. To evaluate thefiltering process we have analyze various type of filter forquantitative analysis of the effect of Gaussian noise to theoriginal image. Simulation is done on MATLAB and results are shown.
Error Detection in 2-bit & 4-bit Multiplier using Parity Predictor Circuit in QCA
Abstract-Error detection is the detection of errors caused by noise or other impairments during the transmission of signal from transmitter to receiver. Logic design errors may occur during simulation and synthesis due to increase in the complexity of CMOS and VLSI circuits. Error detection method can be either systematic or non-systematic. In systematic method, the transmitter sends the original data unit, and a fixed number of check bits or Parity data is been attached to it, which are derived from the same input data unit. In this work, we describe a method of error detection in 4-bit multiplier with parity predictor circuit in QCA tool. 4-bit multiplier is used as a logic in which we detect error according to its input data. The outputs of logic used and the parity predictor are then compared using comparator. If the values do not match, error has occurred. The technique we used is Concurrent error detection using parity predictor circuit.
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